library verilog;
use verilog.vl_types.all;
entity zl_2346_5_vlg_sample_tst is
    port(
        M               : in     vl_logic_vector(1 downto 0);
        RA              : in     vl_logic_vector(1 downto 0);
        Rd              : in     vl_logic;
        Wr              : in     vl_logic;
        clk             : in     vl_logic;
        datain          : in     vl_logic_vector(3 downto 0);
        en              : in     vl_logic;
        rst             : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end zl_2346_5_vlg_sample_tst;
